The present invention relates to a multi-layer ceramic capacitor including side margins provided in a subsequent step, and to a method of producing the multi-layer ceramic capacitor.
Along with miniaturization and achievement of high performance of electronic devices, there have recently been increasingly strong demands for miniaturization and increase in capacity with respect to multi-layer ceramic capacitors used in the electronic devices. In order to meet those demands, it is effective to enlarge internal electrodes of the multi-layer ceramic capacitor. In order to enlarge the internal electrodes, it is necessary to thin side margins for ensuring insulation properties of the periphery of the internal electrodes.
Meanwhile, in a general method of producing a multi-layer ceramic capacitor, it is difficult to form side margins having a uniform thickness because of precision in each step (e.g., patterning of internal electrodes, cutting of a multi-layer sheet, etc.). Thus, in such a method of producing a multi-layer ceramic capacitor, as the side margins are made thinner, it is more difficult to ensure insulation properties of the periphery of the internal electrodes.
Japanese Patent Application Laid-open No. 2012-209539 discloses a technique of providing side margins in a subsequent step. In other words, this technique discloses that a multi-layer chip including internal electrodes exposed to side surfaces is produced, and side margins are then provided to the side surfaces of the multi-layer chip. This makes it possible to form side margins having a uniform thickness, and to ensure insulation properties of the periphery of the internal electrodes also when the side margins are made thinner.